Alliance CAD System is a set of EDA tools and portable cell libraries for VLSI design. It covers a wide range of the standard design flow (from VHDL up to layout). It includes a VHDL simulator, RTL synthesis tools, place and route tools, netlist extractor, DRC, and a layout editor.
|Tags||Scientific/Engineering Electronic Design Automation (EDA)|
|Operating Systems||POSIX Solaris Linux Unix Windows Cygwin|
|Implementation||C C++ Unix Shell YACC|
Release Notes: Many bugs were fixed in Loon and Boog, Graal, and others. Minor Sxlib cell modifications were made to match 0.13 u. Improvements and new features were added to Graal. New features were added to LAX format and VASY.
Release Notes: Many bugs have been fixed. All of the 50 tools have been ported to Cygwin, and the graphical tools are now fully working. A new tool, Mips_asm, was added to convert MIPS ASM to VHDL ROM description. New features were added, such as GDS II with instance names and VASY VHDL subset enhancements. All tutorials have been rewritten or updated. More than fifteen new complete circuit examples were added, from VHDL up to layout (with a MIPS R3000). A new autoconf/automake directory structure is used, which is much more faster than before.
No changes have been submitted for this release.