Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).
The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.
The ReliaFree Project is an alternative to commercial, proprietary reliability, availability, maintainability, and safety (RAMS) analysis software. The ReliaFree Project is an integrated suite of tools. Any number of analyses can be linked together such that an update to one module will result in all linked modules being updated appropriately. This approach provides a closed loop life-cycle with visibility into a product's performance throughout. The same database is used to store field failure data as is used to store design prediction information.
FerFT is a multi-purpose spectral analyzer based on the successive Fourier transformation method. It features an input signal monitor which can sample input signals through a microphone with various sample rates and show them graphically on the panel. It also lets you calculate power spectra successively along with sampled input signals and show them graphically on the panel. Finally, it provides a filter to modify spectra and regenerate signals from them.
BOUML is a UML 2 tool box that allows you to specify and generate code in C++, Java, IDL, and PHP. BOUML is very fast and doesn't require much memory to manage several thousands of classes. BOUML is extensible, and the external tools (named plug-outs) can be written in C++ or Java, using BOUML for their definition as any other program. UML models can be exported to HTML pages, including PNG or SVG graphics.
KiCad EDA is software for the creation of electronic schematic diagrams and printed circuit board artwork. It is a set of four programs and a project manager: Eeschema (schematic entry), Pcbnew (a board editor), Gerbview (a Gerber viewer (photoplotter documents)), and Cvpcb (a footprint selector for components used in the circuit design). Kicad is the project manager. It includes a 3D visualization feature.
FSMDesigner is a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. It uses the Simple-Moore FSM model, guaranteeing efficient fast complex control circuits. It features graphical design of FSMs, support for automatic default transitions, validation of FSMs, a well-defined XML file format, generation of RTL HDL output for both Verilog and VHDL, full scriptability in Python, a modern GUI with undo and redo, simulation mode support, and table based data manipulation.
UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It takes on the well proven openwince jtag tools code. Future plans include conversion of the code base into a library that can be used with other applications. A flexible remote communication protocol that can be used over almost any type of serial link (including TCP/IP) is currently being defined.