127 projects tagged "Electronic Design Automation (EDA)"

No download Website Updated 15 Jul 2010 BOUML

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Pop 117.88
Vit 6.27

BOUML is a UML 2 tool box that allows you to specify and generate code in C++, Java, IDL, and PHP. BOUML is very fast and doesn't require much memory to manage several thousands of classes. BOUML is extensible, and the external tools (named plug-outs) can be written in C++ or Java, using BOUML for their definition as any other program. UML models can be exported to HTML pages, including PNG or SVG graphics.

Download Website Updated 17 Oct 2007 PikLoops

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Pop 20.30
Vit 1.76

PiKLoop generates code to create delays for Microchip PIC microcontrollers. It is a useful companion for Pikdev or Piklab IDE.

Download Website Updated 19 Sep 2007 FerFT

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Pop 14.35
Vit 1.75

FerFT is a multi-purpose spectral analyzer based on the successive Fourier transformation method. It features an input signal monitor which can sample input signals through a microphone with various sample rates and show them graphically on the panel. It also lets you calculate power spectra successively along with sampled input signals and show them graphically on the panel. Finally, it provides a filter to modify spectra and regenerate signals from them.

No download Website Updated 05 Aug 2011 ReliaFree

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Pop 14.42
Vit 1.59

The ReliaFree Project is an alternative to commercial, proprietary reliability, availability, maintainability, and safety (RAMS) analysis software. The ReliaFree Project is an integrated suite of tools. Any number of analyses can be linked together such that an update to one module will result in all linked modules being updated appropriately. This approach provides a closed loop life-cycle with visibility into a product's performance throughout. The same database is used to store field failure data as is used to store design prediction information.

No download Website Updated 16 Mar 2007 The CBOLD Framework

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Pop 14.59
Vit 51.29

The CBOLD framework is a set of C++ classes and related source code for capturing board-level electronic designs. It allows the designer to capture and process an electronic board-level design using a text editor (or IDE) and a C++ compiler. It provides a concise, intuitive notation for schematicless capture of board-level designs. Instead of entering a schematic into an EDA tool, the designer creates a C++ program that describes the design and the desired outputs. When the program is compiled and run, it verifies the legality of the design and writes output files (CAD layout netlist, bill of materials, FPGA constraint files, etc.) to disk. Code primarily consists of definitions of modules, which are analogous to pages of a schematic design.

No download Website Updated 18 May 2012 Scheture

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Pop 65.86
Vit 5.68

Scheture is a hierarchical schematic capture system with built-in netlisters for Spice and Verilog. It has built-in plotting for Postscript, HP PCL and HP GL/2 printers and plotters. It includes a set of symbol primitives, and allows user-defined symbol primitives to allow for extensive customization of primitive properties. The system supports wire buses and iterated instances. The system also supports global pins and implicitly connected pins on a specific sheet. Supported platforms include Solaris and Linux (32- and 64-bit).

Download Website Updated 23 Sep 2007 circdraw

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Pop 24.25
Vit 1.48

circdraw is a program to draw circuit diagrams in LaTeX. It uses a simple language as input, and generates PiCteX code as output. New parts can easily be added.

Download Website Updated 21 Nov 2010 Covered

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Pop 48.26
Vit 7.68

Covered is a Verilog code coverage utility that reads in a Verilog design and a generated VCD/LXT/FST dumpfile from that design and generates a coverage file that can be merged with other coverage files or used to create a coverage report. Covered also contains the GUI coverage report utility that reads in a coverage file to allow interactive coverage discovery. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state/state-transition and assertion coverage.

Download Website Updated 25 Aug 2007 eispice

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Pop 45.30
Vit 3.38

eispice is a clone of the Berkley Spice 3 Simulation Engine with a Python based front-end. It contains a subset of standard spice device models and a set of unique models that are targeted towards PCB level Signal Integrity Simulation.

Download Website Updated 12 Aug 2006 ibistools

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Pop 21.45
Vit 53.35

ibistools is a small set of command-line tools that aid a PCB designer working with IBIS models. It currently consists of a full IBIS v4.1 parser and an IBIS to SPICE translator. IBIS (I/O Buffer Information Specification) is a standard, human-readable, machine-readable format for publishing IC specifications.

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bb_log

A fast and tiny logger for Java.

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CorneliOS

A virtual Web OS.