ChipVault is a chip development program for organizing VHDL and Verilog designs. ChipVault displays designs hierarchically and provides for rapid design navigation and editor launching. ChipVault provides hooks for performing bottom-up tasks such as launching RTL compilers, synthesis, block generation and instantiation, and includes simple to use Revision Control and Issue Tracking systems to help facilitate large group design projects with multiple designers and hundreds of design files. ChipVault is written in Perl and is small, fast, and efficient.
Gnu Circuit Analysis Package is a general purpose circuit simulator. It performs nonlinear DC and transient analysis, fourier analysis, and AC analysis. Spice compatible models for the MOSFET (level 1- 7) and diode are included. This project is not based on Berkeley Spice, but some of the models have been derived from the Berleley models. It was formerly known as 'Al's Circuit Simulator'.
JHDL is a set of FPGA CAD tools which allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist, and interface with backend tools for synthesis, etc. It is an exploratory attempt to identify the key features and functionality of good FPGA tools.