127 projects tagged "Electronic Design Automation (EDA)"

Download Website Updated 16 Oct 2002 Spice Wish

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Pop 19.08
Vit 1.00

SpiceWish is a spice plotter. Features include Trace Place, allowing the easy grouping and comparison of traces against each other, and an editor which allows the re-running of simulations to plot old traces against new for easy comparison.

Download No website Updated 21 Oct 2002 Hardware Simulator for Pesona 16

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Pop 15.30
Vit 65.10

HSP16 is a Pesona-16 (http://www.mysem.com) microprocessor simulation and development environment written in C. HSP16 is capable of simulating and running unmodified Pesona-16 assembly code.

Download No website Updated 01 Feb 2003 tlogsim

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Pop 36.78
Vit 2.26

tlogsim is an extensible graphical logic circuit simulator for GTK 2.

Download Website Updated 22 Jan 2003 asfpga

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Pop 24.68
Vit 1.00

asfpga is an assembler written for use in FPGA design. It can be easily modified for a particular instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version allows you to create a listing file, a memory dump file which can be used in debugging HDL code using $readmemh() or equivalent routine, and a binary file which can be used to program an EPROM.

Download Website Updated 07 Feb 2003 XML PCB Render

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Pop 41.57
Vit 1.00

The XML PCB Renderer takes an XML definition of a printed circuit board (consisting of pads, tracks and components) and renders it to a PNG file suitable for printing onto paper or transparency ready for UV exposure.

Download Website Updated 05 Mar 2003 HDL to HTML conversion script

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Pop 17.41
Vit 1.00

The HDL to HTML conversion script converts either VHDL or verilog to HTML. By default, it creates a left hand menu bar and right hand source display.

Download Website Updated 10 Jun 2011 Platform Independent Petri Net Editor

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Pop 75.12
Vit 5.83

Platform Independent Petri Net Editor (PIPE) creates and analyses Petri Nets quickly, efficiently, and effectively. A key design feature is the modular approach adopted for analysis, enabling new modules to be written easily and powerfully, using built-in data layer methods for standard calculations. Six analysis modules are provided, including Invariant Analysis, State-Space Analysis (deadlock, etc.), and Simulation Analysis and Classification. PIPE adheres to the XML Petri net standard (PNML). The file format for saving and loading Petri Nets is extensible through the use of XSLT, the default being PNML.

No download Website Updated 18 Apr 2003 Verilator

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Pop 34.76
Vit 63.71

Verilator is a cycle based synthesizable Verilog hardware design language compiler. It produces C++ or SystemC output with speeds compariable to commercial products.

Download Website Updated 13 May 2003 Taverna

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Pop 48.79
Vit 1.00

Taverna is a collection of workflow enactment and description components, including a high level language for workflows called Scufl (Simple Conceptual Unified Flow Language), a pure Java object model, parser to populate the model, and a set of views and controllers (including some Swing components to drop into your workflow-enabled applications). In order to actually run workflows you also need the myGrid workflow enactment engine.

Download Website Updated 15 May 2011 Easy Funktion

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Pop 86.39
Vit 9.30

Easy Funktion is 2D function plotter software with an equation solver. It has an office-like GUI frontend and features a built-in pocket calculator, calculating with complex numbers (with special extensions for electronics, e.g. capacitor/inductor impedance), a function to export to spreadsheet software, and an advanced formula editor with automatic formatting.

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bb_log

A fast and tiny logger for Java.

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Project Spotlight

CorneliOS

A virtual Web OS.