Platform Independent Petri Net Editor (PIPE) creates and analyses Petri Nets quickly, efficiently, and effectively. A key design feature is the modular approach adopted for analysis, enabling new modules to be written easily and powerfully, using built-in data layer methods for standard calculations. Six analysis modules are provided, including Invariant Analysis, State-Space Analysis (deadlock, etc.), and Simulation Analysis and Classification. PIPE adheres to the XML Petri net standard (PNML). The file format for saving and loading Petri Nets is extensible through the use of XSLT, the default being PNML.
asfpga is an assembler written for use in FPGA design. It can be easily modified for a particular instruction set. The ultimate goal of this software is to allow a FPGA designer to easily write assembly code for a custom instruction set. The current version allows you to create a listing file, a memory dump file which can be used in debugging HDL code using $readmemh() or equivalent routine, and a binary file which can be used to program an EPROM.
JHDL is a set of FPGA CAD tools which allows the user to design the structure and layout of a circuit, debug the circuit in simulation, netlist, and interface with backend tools for synthesis, etc. It is an exploratory attempt to identify the key features and functionality of good FPGA tools.