I-Nex gathers information for hardware components available on your system and displays it using an user interface similar to the popular Windows tool CPU-Z. It can display information for CPU, GPU, Motherboard, Sound, Hard disks, RAM, Network, and USB, as well as some system information like the hostname, Linux distribution and version, Xorg, GCC, and GLX versions, and Linux Kernel. It can also generate a report on which you can select what to include and optionally send the report to a service such as Pastebin (and others). It also features an option to take a screenshot of the I-Nex window directly from the application.
fpgasm creates bare-metal FPGA designs without Verilog or VHDL. Traditionally, FPGAs are built using proprietary Verilog or VHDL language implementations provided by the vendor. fpgasm is to Verilog and VHDL as assembly language is to C++. It takes you all the way to the netlist, and is not just a translator to Verilog. Because of that, the total "make" time to a working fpga is seconds, not minutes. With fewer than ten reserved words, fpgasm syntax can be mastered in a few minutes. With FPGA assembler, you can focus on understanding the FPGA substrate and how your design should map onto it (instead of figuring out large and complicated tools).
rgbproc-repository is intended for use with Xilinx EDK tools. It consists of many units written in VHDL that can be used to build a design for image/video processing. The backbone is the data bus (called simply RGB) that is used to pass data (typically) from VGA input to VGA/DVI output.
System# is a .NET library intended for the description of real-time embedded systems. It comes with a built-in simulator kernel and a code transformation engine that converts a design into synthesizable VHDL. The main focus is currently the development of FPGA designs. System# not only supports register-transfer-level (RTL) descriptions whose translation to VHDL is straightforward, but is also capable of converting clocked threads with wait statements to a synthesizable VHDL state machine. Furthermore, System# introduces synthesizable transaction-level modeling features. From a technological point of view, it uses reflection and assembly code (CIL) decompilation to reconstruct an abstract syntax tree (AST) from the system design. The AST conforms to SysDOM, a document object model for describing component-based reactive systems. An unparsing stage converts the AST to VHDL. The decompilation process can be instrumented in various ways by attribute-based programming. Furthermore, transformations of the AST itself are possible. This enables implementation of advanced features such as converting clocked threads to finite state machines.
parkverbot is a daemon that prevents hard disk head parking in rotational media. Modern rotational hard disks have a misfeature involving the regular automatic unloading of the heads, measurable by the SMART attribute "Load_Cycle_Count". This causes latency on wake-up amongst other issues (and it cannot always be turned off). The parkverbot daemon will periodically issue small read requests in order to keep the hardware from going to its head-unloaded idle state.